1. Field of the Invention
The present invention relates to high density integrated circuit devices, and more particularly to interconnect structures for multi-level three-dimensional stacked devices.
2. Description of Related Art
High density memory devices are being designed that comprise arrays of flash memory cells, or other types of memory cells. In some examples, the memory cells comprise thin film transistors which can be arranged in three dimensional (3D) architectures.
In one example, a 3D memory device includes a plurality of stacks of strings of memory cells. The stacks include active strips separated by insulating material. The 3D memory device includes an array including a plurality of word lines structures, a plurality of string select structures, and ground select lines, arranged orthogonally over the plurality of stacks. Memory cells including charge storage structures are formed at cross-points between side surfaces of the active strips in the plurality of stacks and the word lines structures.
The 3D memory device is characterized by multiple planes, each of which can include a planar array of active strips. Interference between active strips in adjacent planes, and variations in amounts of interference experienced in different planes can affect device performance.
It is desirable to provide a device structure for reducing the interference and variations in amounts of interference experienced in different planes for three-dimensional memory devices.